1. Field of the Invention
Embodiments of the present invention relate to semiconductor fabrication, and in particular, to methods for reducing semiconductor device defects and enhancing control over semiconductor device geometries and profiles.
2. Background Technology
Current semiconductor device patterning techniques commonly employ a bi-layer antireflective hardmask structure for patterning an underlying layer. FIG. 1 a shows an example of such a structure. In this structure, a semiconductor substrate 10 has formed thereon a silicon oxide gate insulating layer 12 and a polysilicon gate conductive layer 14 that is to be patterned to form a MOSFET gate line. Formed over the gate conductive layer 14 are an antireflective amorphous carbon layer 16, a silicon oxynitride (SiON) capping layer 18, and a photoresist mask including mask portions 20a and 20b. In conventional processing, the photoresist mask pattern is transferred to the SiON layer 18 using a fluorine or chlorine etch chemistry. The pattern is then transferred to the amorphous carbon layer 16 using an oxygen etch chemistry. Finally the pattern is transferred to the polysilicon layer 14 using a fluorine etch chemistry. Because of their similar etch chemistries, the etch of the amorphous carbon typically consumes a portion of the photoresist mask, and the etch of the polysilicon typically consumes a portion of the SiON capping layer.
In the conventional process, anisotropic etching of the polysilicon layer is achieved in part as the result of passivation agents that are released by consumption of the photoresist material during etching of the polysilicon. As shown in FIG. 1b, during etching of the polysilicon layer 14, passivation agents such as nitrogen and carbon enter the atmosphere from the photoresist as it is consumed by the etch and are subsequently deposited on the newly etched sidewalls of the polysilicon layer, where they retard further inward etching and thus contribute to the creation of a vertical sidewall profile. However, as seen in FIG. 1b, the amount of photoresist that remains at a given location at this stage of processing depends on the width of the feature being patterned. For example, in the structure of FIG. 1b, the photoresist mask portion 20b overlying a wide feature remains relatively thick during polysilicon patterning, while the photoresist mask portion 20a overlying a narrower feature is almost completely consumed while a significant amount of polysilicon remains to be patterned. Because the passivation of the polysilicon layer by photoresist components is a highly localized phenomenon, once the photoresist mask portion 20a overlying the narrow feature is consumed, the passivation effect is diminished at that location. Therefore control of profiles becomes more difficult as the dimensions of the features to be patterned are reduced.
Consequently, there is a need for further techniques to reduce patterning defects and to enhance control over device geometries and profiles.
It is therefore an object of the present invention to provide a method of patterning materials such as polysilicon using a bi-layer hardmask in a manner such that profile control is less dependent on the dimensions of the patterned feature.
In accordance with a preferred embodiment of the invention, a photoresist mask is removed from the upper layer of a bi-layer hardmask structure prior to patterning of a polysilicon layer that underlies the bi-layer hardmask structure. Passivation agents are introduced by way of source gasses during etching of the polysilicon, rather than relying on residual photoresist as a source of passivation agents. In this manner control over of patterned features is made less dependent on feature size because the passivation agent concentration at a given location is not dependent on localized photoresist availability.
In accordance with one embodiment of the invention, a semiconductor device is fabricated. Initially a substrate is provided. The substrate has formed thereon a polysilicon layer, a lower hardmask layer, such as amorphous carbon, and an upper hardmask layer, such as SiON. A photoresist mask is then formed on the upper hardmask layer. The upper hardmask layer is then patterned using the photoresist mask as an etch mask to form an upper hardmask. The photoresist mask is then removed from the upper hardmask layer in situ. The lower hardmask layer is patterned using the upper hardmask as an etch mask to form a lower hardmask, and the polysilicon layer is then patterned anisotropically using the lower hardmask as an etch mask while introducing a passivation agent into the chamber from an external source. The patterning of the polysilicon does not utilize any passivation agents emitted from photoresist during patterning since the photoresist was removed at an earlier stage. Therefore greater control over profiles and critical dimensions is provided.
In accordance with other embodiments of the invention, a different patternable material may be patterned using an analogous technique. Such materials include dielectric materials such as silicon oxide and metals such as aluminum.